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1 dual/n-phase buck pwm controller with integrated drivers ISL8126 the ISL8126 integrates two voltage-mode pwm leading-edge modulation control with input feed-forward synchronous buck pwm controllers to control dual independent voltage regulators or a 2-phase single output regulator. it also integrates current sharing control for the power module to operate in parallel, which offers high system flexibility. the ISL8126 integrates an internal linear regulator, which generates ic?s bias voltages fo r applications with only one single supply rail. the internal oscillator is adjustable from 150khz to 1.5mhz, and is able to synchronize to an external clock signal for frequency synchronization and phase paralleling applications. its pll circuit can output a phase-shift-programmable clock signal for the system to be expanded to 3-, 4-, 6-, 12- phas es with desired interleaving phase shift. the ISL8126?s fault spreading feature protects any channel from overloading/stre ssing due to system faults or phase failure. the undervoltage fault protection features are also designed to prevent a negative transient on the output voltage during falling down. this eliminates the schottky diode that is used in some systems for prot ecting the load device from reversed output voltage damage. table 1 summarizes the differences between ISL8126 and ISL8126a. features ?wide v in range operation: 3v to 26.5v - vcc operation from 3v to 5.60v ? excellent output voltage regulation: 0.6v internal reference ? frequency synchronization with programmable phase delay up to 12-phase applications ? fault spreading capability for high system reliability ? digital soft-start with pre-charged output start-up capability ? dual independent channel enable inputs with precision voltage monitor and voltage feed-forward capability - programmable input voltage por and its hysteresis with a resistor divider at en input ? extensive circuit protection fu nctions: output overvoltage, undervoltage, overcurrent prot ection, over-temperature and pre-power-on-reset overvoltage protection option applications ? power supply for datacom/telecom and pol ? paralleling power module ? wide and narrow input voltage range buck regulators related literature ?technical brief tb389 ?pcb land pattern design and surface mount guidelines for qfn packages? table 1. devices reference voltage (v) vsen1+ to vsen1- input impedance ISL8126 0.6 500k ISL8126a 0.7 >2m caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. september 7, 2011 fn7892.0
ISL8126 2 fn7892.0 september 7, 2011 pin configuration ISL8126 (32 ld qfn) top view fb1 vmon1 vsen1- vsen1+ isen1b isen1a vcc boot1 comp2 fb2 vmon2 vsen2- vsen2+ isen2b isen2a vin comp1 iset ishare en/vff1 fsync en/vff2 clkout/refin pgood ugate1 phase1 lgate1 pvcc lgate2 phase2 ugate2 boot2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 33 gnd functional pin descriptions pin number symbol description 1, 9 comp1, comp2 these pins are the error amplifier outputs. they should be connected to fb1, fb2 pins through desired compensation networks when both channels are op erating independently. when vsen1-, vsen2- are pulled within 400mv of vcc, the corresponding error ampl ifier is disabled and its output (comp pin) is high impedance. thus, in multiphase operations, all othe r slave phases? comp pins can tie to the master phase?s comp1 pin (1st phase), which modulates each phase?s pwm pulse with a single voltage feedback loop. while the error amplifier is not disabled, an in dependent compensation network is required for each cascaded ic. 2 iset this pin along with ishare pin are used for mult iple ISL8126 current sharing purposes. when in 2-phase mode (vsen2- pulled within 400mv of vcc), this pi n sources a current which is a combination of 15a constant offset current, current corre ction current (more details on ?current share control in multiphase single output with shared comp voltage? on page 31), and the average of both sensed channel currents. when in dual-output mode, this pi n sources a current, which is a combination of 15a constant offset current, current correction current, and channel 1?s se nsed current. the current sourced out from this pin and an external resistor (riset) set the voltage at th is pin (viset). the riset is recommended to be 10k . a noise decoupling capacitor less than 100pf can be added in parallel with the 10k riset. in the single ic configuration (both 2-phase mode and du al-output mode), this pin can be tied to the ishare pin. 3 ishare this pin is used for current sharing purposes and is configured to the current share bus representing all modules? average current. when in 2-phase mode (vse n2- pulled within 400mv of vcc), this pin sources a current which is a combination of 15a constant offs et current and the average of both sensed channel currents. when in dual-output mode, this pin sources a current, which is a combination of 15a constant offset current and channel 1?s sensed current. the share bus (ish are pins connected together) voltage (vishare ) set by an external resistor (rishare) represents the average current level of all ISL8126 cont roller connected to the current share bus. the share bus impedance rishare should be set as riset/nctrl (riset divided by number of ISL8126 in current sharing controllers). there is a 1.2v threshold for average overcurrent protec tion on this pin. vishare is compared with a 1.2v threshold for average overcurrent protections. when the fault condition on channel 1 is detected or en /vff1 is pulled below its por, ishare is internally pulled to vcc.
ISL8126 3 fn7892.0 september 7, 2011 4, 6 en/vff1, en/vff2 these pins have triple functions. the volt age on en/vff_ pin is compared with a precision 0.8v threshold for system enable to initiate soft-start. with a volt age lower than the threshold, the corresponding channel can be disabled independently. by connecting these pins to the input rail through a voltage resistor divider, the input voltage can be monitored for uvlo (undervoltage lockout) function. the undervoltage lockout and its hysteresis levels can be programmed by these resist or dividers. the voltages on these pins are also fed into the controller to adjust the sawtooth amplitude of each channel independently to realize the feed- forward function. furthermore, during fault (such as overvoltage, over current, and over-temperatu re) conditions, these pins (en/vff_) are pulled low to communicate the information to other cascaded ics. 5 fsync the oscillator switching frequency is adjusted by placing a resistor (rfs) from this pin to gnd. the internal oscillator will lock to an external frequency source if this pin is co nnected to a switching square pulse waveform, typically the clkout signal from another ISL8126 or an external clock. the internal oscillator synchronizes with the leading edge of the input signal. 7 clkout/refin this pin has a dual function depending on the mode in which the chip is operating. it provides a clock signal to synchronize with other ISL8126(s) with its vsen2- pulled within 400mv of vcc for multiphase (3-, 4-, 6-, 8-, 10-, or 12-phase) operation. when the vsen2- pin is not within 400mv of vcc, ISL8126 is in dual mode (dual independent pwm output). the clockout signal of this pin is not available in this mode, but the ISL8126 can be synchronized to external clock. in du al mode, this pin works as the following two functions: 1. an external reference (0.6v target only) can be in place of the channel 2?s internal reference through this pin for ddr/tracking applications. 2. the ISL8126 operates as a dual-pwm controller for two independent regulators with selectable phase degree shift, which is programmed by the voltage level on refin (see ? ddr and dual mode operation ? on page 36). 8 pgood provides an open drain power-good signal when both channels are within 9% of the nominal output regulation point with 4% hysteresis (13%/9%) an d soft-start complete. pgood monitors the outputs (vmon1/2) of the internal differential amplifiers. 32, 10 fb1, fb2 these pins are the inverting inputs of the e rror amplifiers. these pins shou ld be connected to vmon1, vmon2 with the compensation feedback network. no direct connection between fb and vmon pins is allowed. with vsen2- pulled within 400mv of vcc, th e corresponding error amplifier is disabled and the amplifier?s output is high impedance. fb2 is one of the two pins to determine the relative phase relationship between the internal clock of both ch annels and the clkout signal. see table 2 on page 23. 31, 11 vmon1, vmon2 these pins are outputs of the differential amplifiers. they are connected internally to the ov/uv/pgood comparators. these pins should be connected to the fb1, fb2 pins by a standard feedback network when both channels are operating independently. when vs en1-, vsen2- are pulled within 400mv of vcc, the corresponding differential amplifier is disabled and its output (vmon pin) is high impedance. in such an event, the vmon pins can be used as additional monitors of the output voltage with a resistor divider to protect the system against single point of failure, wh ich occurs in the system using the same resistor divider for both of the uv/ov comparator and output voltage feedback. 30, 12 vsen1-, vsen2- these pins are the nega tive inputs of standard unity gain oper ational amplifier for differential remote sense for the corresponding regulator (channels 1 and 2), and should be connected to the negative rail of the load. when vsen1-, vsen2- are pulled within 400mv of vcc, the corresponding error am plifier and differential amplifier are disabled and their outputs are high im pedance. both vsen2+ and fb2 input signal levels determine the relative phases between the internal co ntrollers as well as the clkout signal. see table 2 on page 23. when configured as multiple power modules (each module with independent voltage loop) operating in parallel, in order to implement the current sharing co ntrol, a resistor needs to be inserted between the vsen1- pin and the output voltage negative sense poin t (between vsen1- and lower voltage sense resistor), as shown in the ?typical application circuits? ? multiple power modules in pa rallel with current sharing control ? on page 14. this introduces a correction voltage for the modules with lower load current to keep the current distribution balanced among modules. the module with the highest load current will automatically become the master module. the reco mmended value for the vsen1- resistor is 100 and it should not be large in order to keep the unit gain amplifier input impedance compatibility. a capacitor is also recommended to place in parallel with the 100 . functional pin descriptions (continued) pin number symbol description
ISL8126 4 fn7892.0 september 7, 2011 29, 13 vsen1+, vsen2+ these pins are the positi ve inputs of the standard unity gain op erational amplifier for differential remote sense for the corresponding channel (channels 1 and 2), and should be connected to the positive rail of the load. these pins can also provide precision output volt age trimming capability by pulling a resistor from this pin to the positive ra il of the load (trimming down) or the retu rn (typical vsen1-, vsen2- pins) of the load (trimming up). by setting the resistor divider connected from the output voltage to the input of the differential amplifier, the desired output voltage can be programmed. to minimize the system accuracy error introduced by the input impedance of the differential amplifier, a resistor below 1k is recommended to be used for the lower leg (ros) of the feedback resistor divider. the typical input impedance of vsen+ with respect to vsen- is 500k . with vsen2- pulled within 400mv of vcc, the corresponding error amplifier is disabled and vsen2+ is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the clkout signal. see table 2 on page 23 for details. 28, 14 isen1b, isen2b these pins are the inverting (-) in puts of the current sensing amplifiers to provide r ds(on) , dcr, or precision resistor current sensing together with the isen1a, is en2a pins. refer to ?2-phase operation with rds(on) sensing? on page 9 for r ds(on) sensing set up and ?2-phase operat ion with dcr sensing? on page 8 for dcr sensing set up. 27, 15 isen1a, isen2a these pins are the non-inverting (+) inputs of the current sensing amplifiers to provide r ds(on) , dcr, or precision resistor current sensing together with the isen1b, isen2b pins. 16 vin this pin is the input of the internal linear regulator. it should be tied di rectly to the input rail. the internal linear device is protected against reverse bias generated by the remaining charge of the decoupling capacitor at pvcc when losing the input rail. when used with an external 3.3v to 5v supply, this pin can be tied directly to pvcc to bypass the internal ldo. 25, 17 boot1, boot2 these pins provide the bootstrap biases for the high-side drivers. internal bootstrap diodes connected to the pvcc pin provide the necessary bootstrap charge. it s typical operational voltage range is 2.5v to 5.6v. 24, 18 ugate1, ugate2 these pins provide the ga te signals to drive the high-side devices and should be connected to the mosfets? gates. 23, 19 phase1, phase2 connect these pins to the source of the hi gh-side mosfets and the drain of the low-side mosfets. these pins represent the return path for the high-side gate drives. 22, 20 lgate1, lgate2 these pins provide the drive for the low-si de devices and should be connected to the mosfets? gates. 21 pvcc this pin is the output of the in ternal series linear regulator. it provides the bias for both low-side and high-side drives. its operational voltage range is 3v to 5.6v. a 10f ceramic capacitor is required for decoupling pvcc to ground. 26 vcc this pin provides bias power for the analog circuitr y. an rc filter is recommended between the connection of this pin to a 3v to 5.6v bias (typically pvcc). r is suggested to be a 5 resistor. and in 3.3v applications, the r could be shorted to allow the low end input in concerns of the vcc falling threshold. the vcc decoupling capacitor is strongly recommended to be a low esr ceramic capacitor. this pin can be powered either by the internal linear regulato r or by an external voltage source. 33 gnd the bottom pad is the signal and power ground plane. all voltage levels are referenced to this pad. this pad provides a return path for the low-side mosfet drives and internal power circuitries as well as all analog signals. connect this pad to the circui t ground with the shortest possible path (more than 5 to 6 vias to the internal ground plane, placed on the soldering pad are recommended). functional pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ISL8126crz ISL8126 crz 0 to +70 32 ld 5x5 qfn l32.5x5b ISL8126irz ISL8126 irz -40 to +85 32 ld 5x5 qfn l32.5x5b notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL8126 . for more information on msl please see techbrief tb363 .
ISL8126 5 fn7892.0 september 7, 2011 integrated driver block diagram through shoot- protection bootn ugaten phasen lgaten logic control gate pvcc 10k ? pwmn fault logic 10k ? channels 1 and 2 gate drive 3 ?
ISL8126 6 fn7892.0 september 7, 2011 controller block diagram e/a driver boot1 ugate1 phase1 lgate1 mosfet vsen1+ reset power-on pvcc vmon1 saw1 pwm1 isen1a isen1b vin vsen1- fb1 comp1 soft-start and fault logic channel 1 pwm1 channel 1 current sampling ocp 111 a ch1 en_th i en_hys en/vff1 ov/uv comp1 int. vref ics1 ch1 fault 25 24 23 22 27 28 32 31 29 30 1 4 e/a driver boot2 ugate2 phase2 lgate2 mosfet vsen2+ vmon2 saw2 pwm2 isen2a isen2b vcc vsen2- fb2 comp2 soft-start and fault logic channel 2 pwm1 channel 2 current sampling ocp 111 a ch2 en_th i en_hys en/vff2 ov/uv comp2 ics2 ch2 fault 17 18 19 20 15 14 10 11 13 12 9 6 400mv m/d control clkout/ 7 7-cycle delay m/d control ep int. vref 5 fsync master clock oscillator generator vsen2+ fb2 icsh_corr relative phase control ics2 ics1 average current current share block ishare iset 3 2 7-cycle delay 1.2v avg_ocp icsh_corr i csh_err pvcc 21 internal linear regulator vcc 26 vcc 400mv ss2 ss1 int. vref int. vref current balance circuit ics1 i csh_err i avg_cs ics2 i csh_err i avg_cs current balance circuit avg_ocp 8 pgood pgood circuit en1 en2 en1 en2 vmon1 vmon2 ch1_fault ch2_fault saw1 en/vff1 en/vff2 m/d = 1 (multiphase operation) : i avg_cs = (i cs1 +i cs2 ) / 2 m/d = 0 (dual-output operation) : i avg_cs = i cs1 m/d control refin 16 i avg_cs +15 a
ISL8126 7 fn7892.0 september 7, 2011 table of contents related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 integrated driver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical application circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-phase operation with dcr sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-phase operation with r ds(on) sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dual regulators with dcr sensing and remote sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 double data rate i or ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3-phase regulator with precision resistor sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4 phase operation with dcr sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 multiple power modules in parallel with current sharing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3-phase regulator with resistor sensing and 1 phase regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6 phase operation with dcr sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 voltage feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 overvoltage and undervoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pre-por overvoltage protection (pre-por-ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 over-temperature protection (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 overcurrent protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 current sharing loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 current share control in multiphase single output with shared comp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 current share control loop in multi-module with independent voltage loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 internal series linear and power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 frequency synchronization and phase lock loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 differential amplifier for remote sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 internal reference and system accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 ddr and dual mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 routing ugate, lgate, and phase traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 current sense component placement and trace routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 general powerpad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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ISL8126 8 fn7892.0 september 7, 2011 typical application circuits 2-phase operation with dcr sensing c hfin c bin c f1 pvcc c f2 r cc +3v to +26.5v q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 c out1 r fb1 phase1 v out ISL8126 vcc or gnd remote sensing local sensing (secondary sensing point)
ISL8126 9 fn7892.0 september 7, 2011 2-phase operation with r ds(on) sensing typical application circuits (continued) remote sensing c hfin c bin c f1 pvcc c f2 r cc +3v to +26.5v q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 c out1 r fb1 phase1 v out r fs fsync vin vsen1- r os1 pgood vmon1/2 vsen1+ c sen1 v sense- v sense+ 10 10 z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot2 phase2 vsen2- vsen2+ vin vcc l out2 vcc en/vff1, 2 clkout/refin gnd gnd isen2b fb2 isen1a r isen2 isen1b r isen1 ishare iset r set c f3 vin ISL8126 local sensing (secondary sensing point)
ISL8126 10 fn7892.0 september 7, 2011 dual regulators with dcr sensing and remote sense typical application circuits (continued) vout1 vout2 ISL8126 q1 q2 comp1 fb1 vcc boot1 ugate1 isen1a lgate1 l out1 c hfin c boot1 c out1 r fb1 c f1 phase1 pvcc r fs fsync vin vsen1- r os1 pgood +3.3 to +26.5v vmon1 vsen1+ c sen1 v sense1- v sense1+ 10 10 c f3 z comp1 z fb1 q3 q4 comp2 fb2 boot2 ugate2 isen2a lgate2 l out2 c boot2 c out2 r isen2 r fb2 phase2 vsen2- r os2 vmon2 vsen2+ c sen2 v sense2- v sense2+ 10 10 z comp2 z fb2 vin clkout/refin ishare gnd isen1b c f2 isen2b r isen1 c bin r cc iset vcc r set 2k 2k en/vff2 vin vin en/vff1 vin
ISL8126 11 fn7892.0 september 7, 2011 double data rate i or ii typical application circuits (continued) 0.9v (ddr ii) 0.9v (ddr i) 1.25v v ddq v tt 1.8v (ddr ii) (ddr i) 2.5v ISL8126 q1 q2 comp1 fb1 vcc boot1 ugate1 isen1a lgate1 l out1 c hfin c boot1 c out1 r fb1 c f1 phase1 pvcc r fs fsync vin vsen1- r os1 pgood +3.3 to +26.5v vmon1 vsen1+ c sen1 v sense1- v sense1+ 10 10 c f3 z comp1 z fb1 q3 q4 comp2 fb2 boot2 ugate2 isen2a lgate2 l out2 c boot2 c out2 r isen2 r fb2 phase2 vsen2- r os2 vmon2 vsen2+ c sen2 v sense2- v sense2+ 10 10 z comp1 z fb1 v ddq or vin clkout/refin gnd isen1b c f2 isen2b r isen1 c bin (v ddq /2) r cc ishare iset r set 2k 2k v ddq r vin r*(vtt/0.6-1) 1nf (or tie refin pin to vmon1 pin) notes: 4. setting the upper resistor to be a little higher than r*(vddq/0 .7 - 1) will set the final refin voltage (stead state voltage after soft-start) derived from the vddq to be a little higher than internal 0.6v reference. in this way, the vtt final voltage will use the inter nal 0.6v reference after soft-start. the other way is to add more delay at en/vff1 pin to have channel 2 tracking vddq (check the ? ddr and dual mode operation ? on page 36 for more details). 5. another way to set refin voltage is to connect vmon1 directly to the refin pin. (notes 4, 5)
ISL8126 12 fn7892.0 september 7, 2011 3-phase regulator with precision resistor sensing typical application circuits (continued) c f1 pvcc c f2 r cc q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 phase1 en/vff1,2 vin vsen1- pgood vmon1/2 vsen1+ z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot3 phase2 vsen2- vin vcc l out3 vcc vsen2+ gnd isen2b fb2 isen1a z fb1 c in c f1 pvcc c f2 r cc +3v to +26.5v q1 q2 comp1 fb1 boot1 ugate1 lgate1 l out2 c boot2 c out phase1 v out en/vff1 vin vsen1- pgood vmon1 vsen1+ v sense - v sense + 10 10 c f3 boot2 ugate2 isen2a lgate2 phase2 vcc en/vff2 fsync ishare gnd vmon2 isen1a vin vin clkout/refin ishare r fs fsync clkout/refin c f3 vsen2- vsen2+ fb2 r fb1 r os1 c sen1 vcc gnd r isen3 isen1b vcc isen1b isen2b r isen2 r isen1 r isen1 iset r r iset r r phase 1 and 3 ISL8126 ISL8126 phase 2
ISL8126 13 fn7892.0 september 7, 2011 4 phase operation with dcr sensing typical application circuits (continued) c f1 pvcc c f2 r cc q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 phase1 en/vff1, 2 vin vsen1- pgood vmon1/2 vsen1+ z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot3 phase2 vsen2- vin vcc l out3 vcc vsen2+ gnd isen2b fb2 isen1a z fb1 c in c f1 pvcc c f2 r cc +3v to +26.5v q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out2 c boot2 c out phase1 v out vin r os1 pgood vmon1/2 v sense1- v sense1+ 10 10 c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot4 phase2 vcc l out4 fsync ishare gnd isen2b isen1a vin vin vin clkout/refin ishare r fs fsync clkout/refin c f3 phase 1 and 3 phase 2 and 4 r fb1 r os1 c sen1 2nd divider to avoid single point failure r fb1 vcc vcc isen1b r isen2 r isen4 isen1b r isen3 r isen1 c os iset r iset r r r ISL8126 ISL8126 vsen1,2- vsen1, 2+ fb2 vcc en/vff1, 2 en/vff bus en/vff bus
ISL8126 14 fn7892.0 september 7, 2011 multiple power modules in parallel with current sharing control typical application circuits (continued) c f1 pvcc c f2 r cc1 ISL8126 q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 phase1 en/vff1, 2 vin vsen1- pgood vmon1/2 vsen1+ z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot2 phase2 vin vcc l out2 gnd isen2b isen1a z fb1 c in c f4 pvcc c f5 r cc2 +3v to +26.5v ISL8126 q5 q6 fb1 boot1 ugate1 lgate1 l out3 c boot3 c out2 phase1 v out2 vin pgood vmon1/2 v sense2+ 10 10 c f6 q7 q8 boot2 ugate2 isen2a lgate2 c boot4 phase2 vsen2- vsen2+ vcc l out4 en/vff1, 2 ishare gnd isen2b fb2 isen1a vin vin vin clkout/refin ishare fsync clkout/refin c f3 2-phase 2-phase r fb1 r os1 c sen1 isen1b r isen3 r isen4 isen1b r isen2 r isen1 gnd iset r iset r r r c out1 v out1 v sense1- v sense1+ 10 10 comp1/2 vsen1- vsen1+ z comp2 z fb2 r fb2 r os2 c sen2 v sense2- vsen2- vsen2+ vcc fb2 gnd r csr1 r csr2 vcc v load module #1 module #2 2k 2k 2k 2k en en c csr1 c csr2
ISL8126 15 fn7892.0 september 7, 2011 3-phase regulator with resistor sensing and 1 phase regulator typical application circuits (continued) c f1 pvcc c f2 r cc ISL8126 q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 phase1 vin vsen1- pgood vmon1/2 vsen1+ z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot3 phase2 vsen2- vsen2+ vin vcc l out3 vcc en/vff1, 2 vsen2+ gnd isen2b fb2 isen1a z fb1 c in c f1 pvcc c f2 r cc +3v to +26.5v ISL8126 q1 q2 comp1 fb1 boot1 ugate1 lgate1 l out2 c boot2 c out1 phase1 v out1 en/vff1 vin vsen1- pgood vmon1 vsen1+ 10 10 c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot4 phase2 vcc l out4 en/vff2 fsync ishare gnd vmon2 isen1a vin vin vin clkout/refin ishare r fs fsync c f3 v out2 v sense2- v sense2+ vsen2- vsen2+ 10 10 z fb2 z comp2 c out2 fb2 phase 1 and 3 phase 2 r fb1 r os1 c sen1 vcc gnd r isen3 isen1b r isen4 vcc isen1b isen2b r isen2 r isen1 r isen1 iset r iset r r phase 2 r v sense1+ v sense1- en vout1 en vout2 en vout1
ISL8126 16 fn7892.0 september 7, 2011 6 phase operation with dcr sensing typical application circuits (continued) c in c f1 pvcc c f2 r cc +3v to +26.5v ISL8126 q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out3 c boot3 phase1 en/vff1, 2 vin vsen1- pgood vmon1/2 vsen1+ c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot6 phase2 vsen2- vsen2+ vcc l out6 vcc fsync ishare gnd isen2b fb2 isen1a vin clkout/refin c f1 pvcc c f2 r cc ISL8126 q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out1 c boot1 c out1 phase1 v out1 en/vff1, 2 vin vsen1- r os1 pgood vmon1 vsen1+ v sense1- v sense1+ 10 10 c f3 z comp1 q3 q4 boot2 ugate2 isen2a lgate2 c boot4 phase2 vsen2- vsen2+ vin vcc l out4 vcc fsync ishare gnd isen2b fb2 isen1a z fb1 c sen1 vin clkout/refin c f1 pvcc c f2 r cc ISL8126 q1 q2 comp1/2 fb1 boot1 ugate1 lgate1 l out2 c boot2 phase1 en/vff1,2 vin vsen1- pgood vmon1/2 vsen1+ c f3 q3 q4 boot2 ugate2 isen2a lgate2 c boot5 phase2 vsen2- vsen2+ vin vcc l out5 vcc fsync ishare gnd isen2b fb2 isen1a vin clkout/refin gnd gnd phase 2 and 5 phase 1 and 4 phase 3 and 6 vcc vcc vmon2 r fb1 r os1 r fb1 isen1b isen1b isen1b r isen1 r isen4 r isen2 r isen5 r isen3 r isen6 r iset r iset r iset r gnd vin r r
ISL8126 17 fn7892.0 september 7, 2011 absolute maximum rating s thermal information input voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v signal bias voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v boot/ugate voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +35v phase voltage, v phase . . . . . . . . . . . . . . . . . . . v boot - 7v to v boot + 0.3v boot to phase voltage, v boot - v phase . . . . . . . . . . . -0.3v to vcc +0.3v input, output or i/o voltage . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc +0.3v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101d) . . . . . . . . . . . . . 1kv latch up (tested per jesd-78c ; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical notes 6, 7) ja (c/w) jc (c/w) 32 ld qfn package . . . . . . . . . . . . . . . . . . 31 3 maximum junction temperature . . . . . . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions input voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 26.5v driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v to 5.6v signal bias voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v to 5.6v boot to phase voltage (overcharged), v boot - v phase . . . . . . . . . . . . . <6v temperature ISL8126crz (commercial) . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c ISL8126irz (industrial) . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c (i ndustrial) or 0c to +70c (commercial). parameter symbol test conditions min (note 9) typ max (note 9) units vcc supply current nominal supply vin current i q_vin v in = 20v; vcc = pvcc; f sw = 500khz; ugate, lgate = open 11 15 22 ma nominal supply vin current i q_vin v in = 3.3v; vcc = pvcc; f sw = 500khz; ugate, lgate = open 7 12 14 ma shutdown supply pvcc current i pvcc en = 0v, pvcc = 5v 0.5 1 2.0 ma shutdown supply vcc current i vcc en = 0v, vcc = 3v 5 10 12 ma internal linear regulator current limit threshold i pvcc v in = 6v; pvcc = 4v 320 ma saturated equivalent impedance (note 8) r ldo p-channel mosfet (v in = 5v) 1 pvcc voltage level pvcc i pvcc = 0ma; v in = 12v 5.15 5.40 5.60 v power-on reset rising vcc threshold 2.85 2.97 v falling vcc threshold 2.65 2.75 v rising pvcc threshold 2.85 2.97 v falling pvcc threshold 2.65 2.75 v system soft-start delay (note 8) t ss_dly after pll, vcc, and pvcc pors, and en(s) above their thresholds 192 cycles enable turn-on threshold voltage 0.75 0.8 0.86 v hysteresis sink current i en_hys 0c < t a <+85c 24 30 35 a -40c < t a <+85c 21 30 35 a
ISL8126 18 fn7892.0 september 7, 2011 undervoltage lockout hysteresis (note 8) v en_hys v en_rth = 10.6v; v en_fth = 9v r up = 53.6k , r down = 5.23k 1.6 v sink current i en_sink v enff = 1v 15.4 ma sink impedance r en_sink v enff = 1v 64 oscillator oscillator frequency range 150 1500 khz oscillator frequency r fs = 100k, figure 28 344 377 406 khz total variation vcc = 5v; -40c < t a <+85c -9 +9 % peak-to-peak ramp amplitude v ramp vcc = 5v, v en = 0.8v 1 v p-p linear gain of ramp over v en g ramp g ramp = v ramp /v en 1.25 ramp peak voltage v ramp_peak v en = vcc vcc - 1.4 v peak-to-peak ramp amplitude v ramp v en = vcc = 5.4v, r up = 2k 3 v p-p peak-to-peak ramp amplitude v ramp v en = vcc = 3v; r up = 2k 0.6 v p-p ramp amplitude upon disable v ramp v en = 0v; vcc = 3.5v to 5.5v 1 v p-p ramp amplitude upon disable v ramp v en = 0v; vcc < 3.4v vcc - 2.4 v p-p ramp dc offset v ramp_os 1v frequency synchronization and phase lock loop synchronization frequency vcc = 5v 150 1500 khz pll locking time vcc = 5.4v (2.97v); f sw = 400khz ; 105 s input signal duty cycle range (note 8) 10 90 % pwm minimum pwm off time t min_off 310 345 410 ns current sampling blanking time (note 8) t blanking 175 ns reference channel 1 reference voltage (include error and differential amplifiers? offsets) v ref1 -0c < t a <+70c 0.6 v -0.6 0.6 % -40c < t a <+85c 0.6 v -0.75 0.75 % channel 2 reference voltage (include error and differential amplifiers? offsets) v ref2 -0c < t a <+70c 0.6 v -0.75 0.75 % -40c < t a <+85c 0.6 v -0.8 0.8 % error amplifier dc gain (note 8) r l = 10k, c l = 100pf, at comp pin 98 db unity gain-bandwidth (note 8) ugbw_ea r l = 10k, c l = 100pf, at comp pin 80 mhz input common mode range (note 8) -0.2 vcc - 1.8 v output voltage swing vcc = 5v 0.85 vcc - 1.0 v slew rate (note 8) sr_ea r l = 10k, c l = 100pf, at comp pin 20 v/s electrical specifications recommended operating conditions, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c (i ndustrial) or 0c to +70c (commercial). (continued) parameter symbol test conditions min (note 9) typ max (note 9) units
ISL8126 19 fn7892.0 september 7, 2011 input current (note 8) i fb positive direction into the fb pin 100 na output sink current i comp 3ma output source current i comp 6ma disable threshold (note 8) v vsen- vcc - 0.4 v differential amplifier dc gain (note 8) ug_da unity gain amplifier 0 db unity gain bandwidth (note 8) ugbw_da 5 mhz maximum source current for current sharing (see ?typical application circuit on page 14) i vsen1- vsen1- source current for current sharing when parallel multiple modules each of which has its own voltage loop 350 a output voltage swing (note 8) 0 vcc - 1.8 v input common mode range (note 8) -0.2 vcc - 1.8 v disable threshold (note 8) v vsen- v mon1, v mon2 = tri-state vcc - 0.4 v vsen+ pin input current i vsen+ 0.2 1.16 2.5 a input impedance r vsen+_to _vsen- v vsen+/ i vsen+ , v vsen+ = 0.6v -500 k gate drivers upper drive source resistance r ugate 45ma source current 1.0 upper drive sink resistance r ugate 45ma sink current 1.0 lower drive source resistance r lgate 45ma source current 1.0 lower drive sink resistance r lgate 45ma sink current 0.4 overcurrent protection channel overcurrent limit (note 8) i source vcc = 2.97v to 5.6v 111 a channel overcurrent limit i source vcc = 5v; -0c < t a <+70c 94 111 129 a vcc = 5v; -40c < t a <+85c 89 111 129 a share pin oc threshold v oc_ishare comparator offset included 1.16 1.20 1.22 v current share internal balance accuracy (note 8) vcc = 2.97v and 5.6v, 1% resistor sense, 10mv signal 5 % internal balance accuracy (note 8) vcc = 4.5v and 5.6v, 1% resistor sense, 10mv signal 5 % external current share accuracy (note 8) vcc = 2.97v and 5.6v, 1% resistor sense, 10mv signal 10 % power-good monitor undervoltage falling trip point v uvf percentage below reference point -15 -13 -11 % undervoltage rising hysteresis v uvr_hys percentage above uv trip point 4 % overvoltage rising trip point v ovr percentage above reference point 11 13 15 % overvoltage falling hysteresis v ovf_hys percentage below ov trip point 4 % pgood low output voltage i pgood = 2ma 0.35 v sinking impedance i pgood = 2ma 70 electrical specifications recommended operating conditions, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c (i ndustrial) or 0c to +70c (commercial). (continued) parameter symbol test conditions min (note 9) typ max (note 9) units
ISL8126 20 fn7892.0 september 7, 2011 maximum sinking current (note 8) v pgood <0.8v 10 ma overvoltage protection ov latching trip point en/ff= ugate = latch low, lgate = high 118 120 122 % ov non-latching trip point (note 8) en/ff = low, ugate = low, lgate = high 113 % lgate release trip point en/ff = low/high, ugate = low, lgate = low 87 % over-temperature protection over-temperature trip (note 8) 150 c over-temperature release threshold (note 8) 125 c notes: 8. limits should be considered typi cal and are not production tested. 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications recommended operating conditions, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c (i ndustrial) or 0c to +70c (commercial). (continued) parameter symbol test conditions min (note 9) typ max (note 9) units
ISL8126 21 fn7892.0 september 7, 2011 typical performance curves figure 1. channel 1 accuracy vs temperature f igure 2. channel 2 accuracy vs temperature figure 3. pvcc v-i curve at +25c figure 4. switching frequency vs temperature figure 5. v en/vff1 enable threshold vs temperature figure 6. v en/vff2 enable threshold vs temperature 0.595 0.596 0.597 0.598 0.599 0.600 0.601 0.602 0.603 0.604 0.605 -50 -25 0 25 50 75 100 125 150 temperature (c) ch1_accuracy (v) 0.595 0.596 0.597 0.598 0.599 0.600 0.601 0.602 0.603 0.604 0.605 -50 -25 0 25 50 75 100 125 150 temperature (c) ch2_accuracy (v) 0 1 2 3 4 5 6 0 50 100 150 200 250 300 350 400 450 ipvcc (ma) pvcc (v) t a = +25c v in = 20v v in = 5v v in = 12v v in = 26.5 v in = 3v 343 353 363 373 383 393 403 -50 -25 0 25 50 75 100 125 150 temperature (c) switching frequency (khz) 0.75 0.77 0.79 0.81 0.83 0.85 -50 -25 0 25 50 75 100 125 150 temperature (c) v th _enff1 (v) 0.75 0.77 0.79 0.81 0.83 0.85 -50 -25 0 25 50 75 100 125 150 temperature (c) v th _enff2 (v)
ISL8126 22 fn7892.0 september 7, 2011 modes of operation there are 9 typical operation modes depending upon the signal levels on en/vff1, en/vff2, vsen2+, vsen2-, fb2, and clkout/refin. mode 1: the ic is completely disabled when en/vff1 and en/vff2 are pulled below 0.8v. mode 2: with en/vff1 pulled low and en/vff2 pulled >0.8v (mode 2a), or en/vff1 pulled >0.8v and en/vff2 pulled low (mode 2b), the ISL8126 operates as a single phase regulator. when en/vff1 is pulled low, the ishare pin is pulled to vcc internally. upon en/vff1 >0.8v, there will be current sourcing out from the ishare pin, which represents the channel 1 current plus 15a offset current. mode 3: when vsen2- is used as a negative sense line, both channels? phase shift depends upon the voltage level of clkout/refin. when the clkout/refin pin is within 29% to 45% of vcc, channel 2 delays 0 over channel 1 (mode 3a); when within 45% to 62% of vcc, there is a 90delay (mode 3b); when greater than 62% to vcc, there is a 180 delay (mode 3c). refer to the ? ddr and dual mode operation ? on page 36. mode 4: when vsen2- is used as a negative remote sense line, and clkout/refin is connected to an external voltage ramp lower than the internal soft-start ramp and lower than 0.6v, the external ramp signal will replace channel 2?s internal soft-start ramp to be tracked at start-up, controller operating in ddr mode. the controller will use the lowest voltage among the internal 0.6v reference, the external voltag e in clkout/refin pin and the soft-start ramp signal. channel 1 is delayed 60 behind channel 2. refer to the ? ddr and dual mode operation ? on page 36. mode 5: with vsen2- pulled within 400mv of vcc, fb2 pulled to ground and vsen2+ pulled either to vcc or gnd, the internal channels are 180 out-of-phase and operate in 2-phase single output (mode 5a). the clkout/refin pin also signals out clock with 60 phase shift (rising edge ) relative to the channel 1?s clock signal (falling edge of pwm) for 6-phase operation with two other ISL8126s (mode 5b). when the share pins are not connected to each other for the three ics in sync, two of which can operate in mode 5a. the 3rd ic can be operated in mode 3 to generate 3 independent outputs (mode 5c), or the 3rd ic can also be operated in mode 4 to generate 4 independent outputs (mode 5d). mode 6: with vsen2- pulled within 400mv of vcc, fb2 pulled to vcc and vsen2+ pulled to gnd, the internal channels (as 1st and 3rd phase, respectively) are 240 out-of-phase. the clkout/refin pin signals out 120 relative phases to the falling edge of channel 1?s clock signal to synchronize with the second ISL8126?s channel 1 (as 2nd phase). this allows 3-phase single output configuration to be constructed using two ISL8126s. mode 7: with vsen2- pulled within 400mv of vcc and both of fb2 and vsen2+ pulled to vcc, the internal channel is 180 out-of-phase. the clkout/refin pin signals out (rising edge) 90 relative phase to the channel 1?s clock signal (falling edge of pwm) to synchronize with another ISL8126, which can operate at mode 3, 4, 5a, or 7a. a 4-phas e single output converter can be constructed with two ISL8126s operating in mode 5a or 7a (mode 7a). if the share bus is not connected between ics, each ic could generate an independent output (mode 7b). when the second ISL8126 operates as two independent regulators (mode 3) or in ddr mode (mode 4), then a three independent output system is generated (mode 7c). both ics can also be constructed as a 3-phase converter (0, 90, and 180, not an equal phase shift for 3-phase) with a single phase regulator (270). mode 8 : the output clkout sign al allows expansion for 12-phase operation with the cascaded sequencing, as shown in table 2. no external clock is required in this mode for the desired phase shift. mode 9: with an external clock, the part can be expanded for 5, 7, 8, 9 10 and 11 phase single ou tput operation with the desired phase shift. figure 7. en/vff1 hysteresis current vs temperature figure 8. en/vff2 hysteresis current vs temperature typical performance curves (continued) 25 27 29 31 33 35 -50 -25 0 25 50 75 100 125 150 temperature (c) i en _ff1_hyst (a) 25 27 29 31 33 35 -50 -25 0 25 50 75 100 125 150 temperature (c) i en _ff2_hyst (a)
ISL8126 23 fn7892.0 september 7, 2011 table 2. 1st ic (i = input; o = output; i/o = input and output, bi-direction) modes of operation output (see description for details) operation mode of 2 nd ic operation mode of 3 rd ic mode en/ vff1 en/ vff2 vsen2- (i) fb2 (i) vsen2+ (i) clkout/refin wrt 1st (i or o) ishare (i/o) represents which channel(s) current 2nd channel wrt 1st (o) (note 10) 1 <0.8v <0.8v - - - - - - - - disabled 2a <0.8v >0.8v active active active - n/a - - - single phase 2b >0.8v <0.8v - - - - 1 st channel - - - single phase 3a >0.8v >0.8v 0.8v >0.8v 0.8v >0.8v 62% of vcc (i) 1 st channel 180 - - dual regulator 4 >0.8v >0.8v 12) notes: 10. ? 2nd channel wrt 1st ? is referred to as ?channel 2 lag channel 1 by the degrees spec ified by the number in the corresponding table cells?. for exam ple, 90 with 2nd channel wrt 1st means channel 2 lags channel 1 by 90; -60 with 2nd channel wrt 1st means channel 2 leads channel 1 by 60. 11. all en/vff pins are tied together.
ISL8126 24 fn7892.0 september 7, 2011 vsen2- vsen2+ vmon2 uv/ov 400mv vcc figure 9. simplified relative phases control diff error amp2 comp2 amp2 comp2 channel 1 pwm control block channel 2 pwm control block v ref2 = v ref fb2 clock generator and relative phases control clkout/refin ch1 ug (1 st ic) d 1-d clkout (1 st ic) ch2 ug (1 st ic) ch2 ug (2 nd ic) 50% d d 180 d ch1 ug (2 nd ic) 90 180 ch1 ug (1 st ic) d 1-d clkout (1 st ic) ch2 ug (1 st ic) ch2 ug(2 nd ic, off, en/vff2 = 0) 50% d 240 ch1 ug (2 nd ic) 120 3-phase timing diagram (mode 6) d 1-d 120 90 4 phase timing diagram (mode 7a)
ISL8126 25 fn7892.0 september 7, 2011 functional description initialization initially, the ISL8126 power-on reset (por) circuits continually monitor the bias voltages (pvcc and vcc) and the voltage at the en/vff pin. the por function initiates soft-start operation 192 clock cycles after the following conditions are met: ? vcc and pvcc voltages exceed their por thresholds. ? pll locking time has expired. ? en/vff pin voltage is pulled to be above 0.8v. ? for channel 1 only, ishare voltage must fall below 70% (typical) of vcc. ishare is also pulled to vcc when channel1 detects fault conditions or en/vff1 is below its por threshold. ishare is released from vcc after en/vff1? s voltage higher than its por threshold for 16 switching cycles; therefore, there is 176 cycles delay from ishare falls to 0.7*vcc to the beginning of soft start. during shutdown or fault conditions, the soft-start is reset quickly while ugate and lgate change states immediately (<100ns) upon the input drop below falling por. the soft-start initialization circuit is shown in figure 10. the en/vff pin can be used as a voltage monitor and to set desired hysteresis with an internal 30 a sinking current going through an external resistor divider. the sinking current is disengaged after the system is enabled. this feature is especially designed for applications that require higher input rail por for better undervoltage protection. for example, in single-phase 12v input applications, r up = 53.6k and r down = 5.23k will set the turn-on threshold (v en_rth ) to 10.6v and turn-off threshold (v en_fth ) to 9v, with 1.6v hysteresis (v en_hys ). there is an internal transistor, which will pull down the en/vff pin under fault conditions. the multiphase system can immediately turn off all ics under fault conditions of one or more phases by pulling all en/vff pins low. thus, no bouncing occurs among channels at fault and no single phase could carry all current and be over stressed. the pull-up resistor (r up ) should be scaled to sink no more than 5ma current to the en/vff pin. essentially, the en/ff pins cannot be directly connected to vcc. voltage feed-forward other than used as a voltage mo nitor described in the previous section, the voltages applied to the en/vff pins are also fed to figure 10. soft-start initialization logic vcc por pvcc por en/vff1 por soft-start high = above por; low = below por of channel 1 and 176 vcc por pvcc por en/vff2 por soft-start of channel 2 and pll locking cycles 192 cycles + - comparator ishare 0.7*vcc figure 11. typical 4-phase with fault handshake en/vff1 en/vff2 2-phase en/vff1 en/vff2 2-phase ISL8126 ISL8126 r up r down vin r up v en_hys i en_hys n phase ? --------------------------------------------------- = figure 12. simplified enable and voltage feedforward circuit 0.8v i en_hys = 30 a r up r down en_por r down r up v ? en_ref v en_fth v en_ref ? ------------------------------------------------------ - = v en_fth v en_rth v en_hys ? = vin g ramp = 1.25 limiter sawtooth amplitude v ramp max (v cc_ff g ramp , vcc - 1.4v - v ramp_offset ) = ( v ramp ) en/vff ov, ot, oc, and pll locking faults (only for en/vff1) r up v en_hys nx i en_hys ------------------------------- - = system delay v cc_ff vcc 0.8v v ramp_offset = 1.0v vcc - 1.4v lower limit upper limit (ramp offset) where n is number of en/vff pins connected together v cc_ff max(0.8v, v enff ) =
ISL8126 26 fn7892.0 september 7, 2011 adjust the amplitude of each channel?s individual sawtooth. this helps to maintain a constant gain ( ) contributed by the modulator and the input voltage to achieve optimum loop response over a wide input voltage range. the amplitude of each channel?s sawtooth is set to 1.25 times the corresponding en/vff voltage upon its enable (above 0.8v). the sawtooth ramp offset voltage is 1v, and the peak of the sawtooth is limited to vcc - 1.4v. this allows a maximum peak-to-peak amplitude of sawtooth ramp to be vcc - 2.4v. a constant voltage (0.8v) is fed into the ramp generator to maintain a minimum peak-to-peak ramp. with vcc = 5.4v, the ramp has an allowable maximum peak-to-peak voltage of 3v and minimum of 1v. therefore, the feed-forward voltage effective range is typically 3x. a 192 cycle delay is added after the system reaches its rising por and prior to the soft-start. the rc timing at the en/vff pin should be sufficiently small to ensure that the input bus reaches its static state and the internal ramp circuitry stabilizes before soft-start. a large rc could cause the internal ramp amplitude not to synchronize with the input bus voltage during output start-up or when recovering from faults. it is recommended to use open drain or open collector to gate this pin for any system delay, as shown in figure 12. soft-start the ISL8126 has two independent digital soft-start circuitry with fixed 1280 switching cycles. refer to figure 13. the full soft-start time from 0v to the target value can be estimated using equation 1. the ISL8126 has the ability to work under a pre-charged output (see figure 14). the output voltage would not be yanked down during pre-charged start-up. if th e pre-charged output voltage is greater than the final target level but lowered to 120% setpoint, the switching will not start until the fb voltage reduces to the internal soft-start signal or the end of the soft-start is declared (see figure 15). power-good both channels share the same pgood output. either of the channels indicating out-of-regulation will pull-down the pgood pin. the power-good comparators monitor the voltages on the vmon pins. the trip points are shown in figure 16. states of both en/vff1 and en/vff2 have impact on the pgood signal. if one of the vmon pins? voltage is out of the threshold window, pgood will not pull low until the faul t presents for three consecutive clock cycles. g m vin d max v ramp ? ? = t ss 1280 f sw ------------- - = (eq. 1) vmon 0.0v t ss 1280 f sw ------------- - = first pwm pulse -100mv t ss_dly 192 f sw ------------- - = figure 13. soft-start with vout = 0v ss settling at vref + 100mv pre-charged level vmon first pwm pulse -100mv ss settling at vref + 100mv figure 14. soft-start with ou tput pre-chareged level < final target level ov = 113% vout target voltage first pwm pulse figure 15. soft-start with vout below ov but above final target voltage
ISL8126 27 fn7892.0 september 7, 2011 overvoltage and undervoltage protection the overvoltage (ov) and undervoltage (uv) protection circuitry monitor the voltage on the vmon pins. ov protection is active upon vcc por. an ov condition (>120%) would latch ic off (the high-side mosfet to latch off permanently; the low-side mosfet turns on immediately at the time of ov trip and then turns off after the vmon drops below 87%). the en/vff and pgood are also latched low at ov event. the latch condition can be reset only by recycling vcc. in dual/ddr mode, each channel is responsible for its own ov event with the corresponding vmon as the monitor. in multiphase mode, both channels respond simultaneously when either triggers an ov event. there is another non-latch ov protection (113% of target level). at the condition of en/vff low and the output over 113% ov, the lower side mosfet will turn on until the output drops below 87%. this is to protect the overall power trains in case of only one channel of a multiphase system detecting ov. the low-side mosfet always turns on at the conditions of en/vff = low and the output voltage above 113% (all vmon pins and en/vff pins are tied together) and turns off after the output drops below 87%. thus, in a high phase count app lication (multiphase mode), all cascaded ics can latch off simultaneously via the en/vff pins (en/vff pins are tied together in multiphase mode), and each ic shares the same sink current to reduce the stress and eliminate the bouncing among phases. the uv functionality is not enabled until the end of soft-start. in a uv event, if the output drops below -13% of the target level due to some reason (cases when en/vff is not pulled low) other than ov, oc, ot, and pll faults, the lower mosfets will be turned on for ~345ns for each switching cycle to avoid high negative voltage ringing until the un condition is removed. pre-por overvoltage protection (pre-por- ovp) when both the vcc and pvcc are below pors (not including en por), the ugate is low and lgate is floating (high impedance). en/vff has no control on lgate when vcc and pvcc are below their pors. when vcc and pvcc are above their pors, the lgate would not be floating but togg ling with its pwm pulses. an internal 10k resistor, connected in between phase and lgate figure 16. power-good threshold window -13% -9% v ref +9% +13% vmon1, 2 pgood +20% pgood1, 2 pgood latch off + - en/vff1 0.8v en1 + - en/vff2 0.8v en2 + - vmon1 v ref pgood1 ch1 soft-start done + - vmon2 v ref pgood2 ch2 soft-start done pgood1 en1 pgood2 en2 pgood1 pgood2 after 120% ov figure 17. force lgate high logic en/vff1 force vmon1 lgate1 high 113% 87% en/vff2 force vmon2 lgate2 high 113% 87% vmon1>120% vmon2 > 120% multiphase mode = high or or or and and and figure 18. pgood timing under uv and ov uv ov latch 3 cycles vout pgood ugate and en/vff latch low 3 cycles 120%
ISL8126 28 fn7892.0 september 7, 2011 nodes, implements the pre-por-ovp circuit. the output of the converter that is equal to ph ase node voltage via output inductors is then effectively clamped to the low-side mosfet?s gate threshold voltage, which provides some protection to the load if the upper mosfet(s) is shorted during start-up, shutdown, or normal operations. for comp lete protection, the low-side mosfet should have a gate thresh old that is much smaller than the maximum voltage rating of the load. the pre-por-ovp works against pre-biased start-up when pre- charged output voltage is high er than the threshold of the low-side mosfet, however, it can be disabled by placing a resistor from lgate to ground. the resistor value can be estimated from equation 2. the resistor value should be as large as possible to minimize power dissipation, while providing sufficient margin for the internal 10k and mosfet?s vth tolerances. for example, a 2k resistor is recommended for applications using logic-level mosfet with the maximum pre-biased voltage less than 5v. over-temperature protection (otp) when the junction temperature of the ic is greater than +150c (typically), both en/vff pins pull low to inform other cascaded channels via their en/vff pins. all connected en/vffs stay low and release after the ic?s junc tion temperature drops below +125c (typically), with a +25c hysteresis (typical). inductor current sensing the ISL8126 supports inductor dcr sensing, mosfet?s r ds(on) sensing, or resistive sensing techniques. the circuits shown in figures 19, 20, and 21 represent one channel of the controller. this circuitry is identical for both channels. note that the common mode input voltage range of the current sense amplifiers is vcc - 1.8v. therefore, the r ds(on) sensing must be used for applications wi th output voltage greater than vcc - 1.8v. for example, when vcc = 5.4v, the inductor dcr and the resistive sensing configurations can be used for output voltage less than 3v. for higher output voltage, r ds(on) sensing configuration must be used. inductor dcr sensing an inductor?s winding is characteri stic of a distributed resistance as measured by the dcr (direct current resistance) parameter. consider the inductor dcr as a separate lumped quantity, as shown in figure 19. the inductor current, i l ; will also pass through the dcr. equation 3 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across th e inductor extracts the dcr voltage, as shown in figure 19. the voltage on the capacitor v c , can be shown to be proportion al to the inductor current i l , see equation 4. if the r-c network components ar e selected such that the rc time constant (= r*c) matches the inductor time constant (= l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr, i.e. proportional to the inductor current. the value of r should be as small as feasible for best signal-to-noise ratio. make sure the resistor package size is appropriate for the power dissipated and include this loss in efficiency calculations. in calc ulating the minimum value of r, the average voltage across c (which is the average i l dcr product) is small and can be neglected. therefore, the minimum value of r may be approximated using equation 5. where p r-pkg is the maximum power dissipation specification for the resistor package and p is the derating factor for the same parameter (eg.: p r-pkg = 0.063w for 0402 package, p = 80% @ +85c). k is the marg in factor, also to limit r 10k v pre biased max () ? v th min () ------------------------------------------------ 1 ? ---------------------------------------------------------- < (eq. 2) figure 19. dcr sensing configuration i cs n () - + isen(n)a sample & hold isl8216 v in isen(n)b ugate(n) r isen(n) dcr l inductor r v out c out (ptc) - + v c (s) c i l s () - + v l phase(n) lgate(n) internal circuit isen v l i l sl dcr + ? () ? = (eq. 3) v c s l dcr ----------- - ? 1 + ?? ?? dcr i l ? () ? src 1 + ? () ----------------------------------------------------------------- = (eq. 4) r min dv in max ? v out ? () ? 2 1d ? () v out 2 ? + kp ? rpkg ? p ? ------------------------------------------------------------------------------------------------------ = (eq. 5)
ISL8126 29 fn7892.0 september 7, 2011 temperature raise in the resistor package, recommend using 0.4. once r min has been calculated, solve for the maximum value of c using equation 6 : and choose the next-lowest readily available value. then substitute the chosen value into the same equation and re-calculate the value of r. ch oose the 1% resistor standard value closest to this re-calculated value of r. for example, when v in_max = 14.4v, v out = 2.5v, l = 1h and dcr = 1.5m , with 0402 package equation 5 yields r min of 1476 and equation 6 yields c max of 0.45f. by choosing 0.39f and recalculating the resistor it yields 1.69k . with the internal low-offset cu rrent amplifier, the capacitor voltage v c is replicated across the sense resistor r isen . therefore, the current out of isen(n)b pin, i sen , is proportional to the inductor current. after 175ns blanking period with respect to the falling edge of the pwm pulse of each channel, the i sen current is filtered and sampled for 175ns. the sampling current i cs then can be derived as shown by equation 7: where i l is the inductor dc current, f sw is the switching frequency, and t min_off is 350ns. resistive sensing for accurate current sense, a dedicated current-sense resistor rsense in series with the output inductor can serve as the current sense element (see figure 20). this technique is more accurate, but reduces overall converter efficiency due to the additional power loss on the current sense element rsense. equation 8 shows the sampling current, i cs , when using sensing resistor similar to dcr current sensing approach, the resistive sensing approach can be used with output voltage less than vcc - 1.8v. mosfet r ds(on) sensing the controller can also sense the channel load current by sampling the voltage across the synchronous mosfet r ds(on) (see figure 21). the amplifier is ground-reference by connecting the isen(n)a pin to the source of the synchronous mosfet. isen(n)b pin is connected to the synchronous mosfet?s drain through the current sense resistor r isen . the voltage across r isen is equivalent to the voltage drop across the r ds(on) of the lower mosfet while it is conducting. the resulting current out of the isen(n)b pin is proportional to the channel current i l . equation 9 shows the sampling current, i cs , when using mosfet r ds(on) sensing. both inductor dcr and mosfet r ds(on) value will increase as the temperature increases. therefore the sensed current will increase as the temperature of the current sense element increases. in order to compensate the temperature effect on the sensed current signal, a positive temperature coefficient (ptc) resistor can be selected for the sense resistor r isen . overcurrent protection for overload and hard short condition, the overcurrent protection reduces the regulator rms output current much less than full load by putting the controller into hiccup mode. a delay time, equal to 3 soft-start intervals, is inserted to allow the disturbance to be cleared out. after the delay time, the controller then initiates a soft-start interval. if the output voltage comes up and returns to the regulation, pgood transitions high. if the oc trip is c max l r min dcr ? ----------------------------- - = (eq. 6) ics i l v out l ------------ - 1d ? 2f sw -------------- - t min_off ? ?? ?? ? + ?? ?? ?? dcr ? r isen ------------------------------------------------------------------------------------------------------- - = (eq. 7) figure 20. sense resistor in series with inductor i cs n () - + isen(n)a sample and hold isl8216a v in isen(n)b ugate(n) r isen(n) rsense l v out c out i l phase(n) lgate(n) internal circuit isen ics il v out l ------------ - 1d ? 2f sw -------------- - t min_off ? ?? ?? ? + ?? ?? ?? rsense ? r isen ------------------------------------------------------------------------------------------------------------------- - = (eq. 8) figure 21. mosfet r ds(on) current-sensing circuit - + r isen sample and hold ISL8126 internal circuit external circuit v in n-channel mosfets - + i l x r ds on () i l (ptc) isen(n)a isen(n)b isen i cs n () i cs i l v out l ------------ - 1d ? 2f sw -------------- - t min_off ? ?? ?? ? + ?? ?? ?? r ds on () ? r isen ---------------------------------------------------------------------------------------------------------------- - = (eq. 9)
ISL8126 30 fn7892.0 september 7, 2011 exceeded during the soft-start interval, the controller pulls en/vff low again. the pgood signal will remain low and the soft-start interval will be allowed to expire. another soft-start interval will be initiated after the delay interval. if an overcurrent trip occurs again, this same cycle repeats until the fault is removed. the ocp function is enabled at start-up. the ISL8126 monitors 2 signals: sampled channel current, ics, and ishare voltage for overcurrent protection. channel current ocp each sampled channel current, i cs , is compared to 111a (typ.) for the ocp trip point. the channel over current trip point can be set by using r isen value such that the over current trip point corresponds to the channel sensin g current, ics, of 111a. for dcr current sensing, equation 7, and r ds(on) current sensing, equation 9, the r isen can be estimated from equations 10 and 11, respectively. without temperature compensation, the ocp trip point should be evaluated based on the dcr or mosfet r ds(on) values at the maximum device?s temperature. while configured as multi-phase operation (vsen2- > vcc- 400mv), the channel ocp has 7 clock cycles delay before entering hiccup mode. in dual-output operation, the 7-clock cycle delay on channel 2 is bypassed so the circuit responds to over current condition immediately. in this mode, the 7-clock cycle delay in channel1 is still active. the fast o cp response on channel1 will be rely on the ocp on ishare pin where the voltage on this pin represents the channel1 current. during soft-start period with vmon1 less than 0.4v, the ocp threshold on the sampled channel current, ics, of both channels are increased to 222a (typ.) to compensate the in-rush current. ishare ocp refer to the block diagram, ishare pin sources out a current iavg_cs with 15a offset. in the 2-phase mode, iavg_cs is the average of both channels 1 and 2 sampled currents as calculated in equation 12. while in the dual-output mode, iavg_cs is a copy of channel1?s sampled current. in multiphase operation, the vishare represents the average current of all ISL8126 and compares with the ishare pin precision 1.2v threshold to determine the ov ercurrent condition. at the same time, each channel has additional overcurrent trip point at 111a with 7-cycle delay for channel overcurrent protection. this scheme helps protect against loss of channel( s) in multi-phase mode so that no single channel could carry excessi ve current in such event. with r ishare = 10k , it would make the channel current ocp and ishare ocp trip at the same over current level; (111a + 15a) x 10k = 1.26v. note that it is not necessary for the r ishare to be scaled to trip at the same level as the 111a ocp comparator if the application allows. for instance, when channel 1 operates independently, the oc trip set by 1.2v comparator ca n be lower than 111a trip point. to set the ishare ocp in the multi-phase configuration, the r isen must be determined first by using equations 10 or 11. the ioc in equations 10 or 11 is overcurrent for each phase, which is approximately ioc_tota l/number of phases. upon determining r iset , equations 7, 8, 9, and 11 can be used to determine ishare ocp, as shown in equation 12. where n cntl is the number of the ISL8126 controllers in parallel or multiphase operations. for the r isen chosen for ocp setting, the final value is usually higher than the number calculated from equation 9. the reason for which is practical, especially for low dcr applications since the pcb and inductor pad soldering resistance would have large effects in total impedance, affecting the dcr voltage to be sensed. current sharing loop when the ISL8126 operates in 2-phase mode (vsen2- is pulled within vcc - 400mv), the current control loop keeps channel 1 and channel 2 currents in balance. the sensed currents from both channels are combined to create an average current reference (iavg), which represents average current of both channel currents. the signal iavg is then subtracted from the individual sensed current (ics1 or ics2) to produce a current correction signal for each channel. the block diagram of current sharing control circuit is shown in figure 22. when both channels operate independently, the average function is disabled, and the current correction block of channel 2 is also disabled. the i avg_cs is channel 1 sensed current i cs1 . channel 1 makes any necessary current correction by comparing the voltages at iset and ishare pins (for 3-phase, two ISL8126s configuration). when the share bus does not connect to other ics, the iset and ishare pins can be shorted toge ther and grounded via a single resistor to ensure zero share error. r isen ioc v out l ------------ - 1d ? 2f sw -------------- - t min_off ? ?? ?? ? + ?? ?? ?? dcr ? 111 a ------------------------------------------------------------------------------------------------------------- = (eq. 10) r isen ioc v out l ------------ - 1d ? 2f sw -------------- - t min_off ? ?? ?? ? + ?? ?? ?? r ds on () ? 111 a --------------------------------------------------------------------------------------------------------------------- - = (eq. 11) iavg_cs ics1 ics2 + 2 -------------------------------- - = (eq. 12) r ishare 1.2v i avg_cs 15 a + () i i1 = n cntl ----------------------------------------------------------------- = r iset r ishare n cntl ? = (eq. 13)
ISL8126 31 fn7892.0 september 7, 2011 current share control in multiphase single output with shared comp voltage in multiphase/multi-ic implementation with one single error amplifier for the voltage loop, all comp pins must be tied together. therefore, all other cha nnels? error amplifiers that are not used in voltage loop should be disabled with their corresponding vsen- pulled to vcc, as shown in figure 23. for current sharing purposes, all is hare pins must also be tied together. the share bus (v ishare ) represents the average current of all ISL8126s connected to the same ishare bus. the ishare pin sources a copy of the i avg_cs with 15a offset (i avg_cs equals to i avg or i cs1 depending upon the configuration). the iset pin sources out a copy of i avg_cs , i csh_err and 15a offset. i csh_err on the iset pin makes the voltage at the iset pin track the voltage at the ishare pin with 20mv offset. thus, i csh_err represents the difference of an individual ISL8126 current to the average current (ishare). the current share error signal (i csh_err ) is then fed into the current correction block to adjust each channel?s pwm pulse accordingly. if one single external resistor is used as r ishare connecting the ishare bus to ground for all the ics in parallel, r ishare should be set equal to r iset /n ctrl (where n cntl is the number of the ISL8126 controllers in parallel or multiphase operations), and the share bus voltage (v ishare ) set by the r ishare , represents the average current of all channels. r ishare can also be set by putting one resistor in each ic?s ishare pin and using the same value with r iset (r ishare = r iset ), which results in the total equivalent resistance value as r iset /n ctrl . the current share function provides at least 10% overall accuracy between ics, 5% within the ic wh en using a 1% resistor to sense a 10mv signal. the current share bus works for up to 12-phase. current correction block figure 22. simplified current share and internal balance implementation ishare current mirror block i avg_cs +15a iset v error1 + - i cs1 - error amp 1 v error2 + - i cs2 - error amp 2 i avg_cs 400mv vcc vsen2- - - + i csh_err share bus r iset r ishare r ishare =r iset /n ctrl ishare = i avg_cs + 15a i avg_cs = i avg or i cs1 i avg = (i cs1 + i cs2 ) / 2 i csh_err i avg_cs +15a i avg_cs current mirror block vsen1- vsen1+ vmon1 current correction block + current correction block i csh_err i csh_err 20mv iset = i avg_cs + 15a + i csh_err
ISL8126 32 fn7892.0 september 7, 2011 current share control loop in multi-module with independent voltage loop the power module controlled by ISL8126 with its own voltage loop can be paralleled to supply one common output load with its integrated master-slave current sharing control, as shown in the ?typical application circuits? on page 14. a resistor r csr and a capacitor c csr need to be inserted between vsen1- pin and the lower resistor of the voltage se nse resistor divider for each module. with this resistor, the co rrection current sourcing from the vsen1- pin will create a voltage offset to maintain even current sharing among modules. the recommended value for the vsen1- resistor r csr is 100 and it should not be large in order to keep the unity gain amplifier input pin impedance compatibility. the maximum source current from the vsen1- pin is 350a, which is combined with r csr to determine the current sharing regulation range. the generated correction voltage on r csr is suggested to be within 5% of vref (0.6v) to avoid fault triggering of uv/ov and pgood during dynamic events. the value for c csr can be estimated from equation 14. where f sw is switching frequency. it is recommended to have 3 analog signals: clkout-sync, ishare, and en/vff for communic ation among the paralleled modules. all the modules are synchronized and the phase shift can also be configured to optimal to reduce the input current ripple by interleaving effects. the connections of these three wires allows the system to be started at the same time and achieve good current balance in st art-up without overcurrent trip. internal series linear and power dissipation the vin pin is connected to pvcc with an internal series linear regulator. the internal linear regulator?s input (vin) can range between 3v to 26.5v. pvcc pin is the output of the internal linear regulator and it provides power for both the internal mosfet drivers. the pvcc and vin pins should have the recommended bypass ceramic capacitors (10f) connected to gnd for proper operation. pvcc can be used to bias the ic analog circuitry, vcc, by connecting vcc to pvcc pin. the vcc pin should be connected to the pvcc pin with an rc filter to prevent high frequency driver switching noise into the analog circuitry. when the v in drops below 5.0v, the pass element will saturate; pvcc will track v in with a dropout of the linear regulator. when used with an external supply less than 5v, the pvcc pin is recommended to be tied directly to v in . the ldo is capable of supplying 250ma with regulated 5.4v output. in 3.3v input applications, when the vin pin voltage is 3v, the ldo can still supply 150ma while maintaining ldo output voltage higher than vcc falling threshold to keep the ic operating. figure 3 shows the typical v-i curve of the internal ldo. note that the power dissipation in the device should not be exceeded the package thermal limit. the power dissipation inside the ic can be estimated with equations 14 and 16. where the gate charge (q g1 and q g2 ) is defined at a particular gate to source voltage (v gs1 and v gs2 ) in the corresponding mosfet datasheet; i q_vin is the driver?s total quiescent current with no load at drive outputs; n q1 and n q2 are number of upper and lower mosfets, respectively. r iset2 figure 23. simplified 6-phase single output implementation ishare iset share bus r iset1 r ishare1 ISL8126 1 vsen1/2- com1/2 ishare iset r iset3 r ishare3 ISL8126 3 vsen1/2- com1/2 ishare iset r ishare2 ISL8126 2 en/vff1,2 com1/2 vsen1+ vsen1- r ishare_ = r iset_ vcc vcc en/vff1,2 en/vff1,2 clkout clkout fsync fsync with voltage loop vin r en/vff_low r en/vff_up c csr 35 r csr f sw ------------------------------- = (eq. 14) figure 24. internal regulator implementation 5v z1 3v to 26.5v 2.65v to 5.6v pvcc vin vcc z2 2 1f 10f
ISL8126 33 fn7892.0 september 7, 2011 it is recommended that operating junction temperature of the ic to be less that +135c. this limits the maximum power dissipation inside the ic. equations 14, 16 and ja can be used to estimate the maximum total gate change, q g_total . the power dissipation inside the ic should be evaluated at the maximum ambient temperature. in addition, the total gate change and the operating switching frequency should not load the internal ldo beyond the current limit thresh old. figure 27 provides the guideline of the allowed maximum gate charge. to keep the ic within its operating temperature range, an external power resistor could be used in series with the vin pin to bring the heat out of the ic, or and external ldo could be used when necessary. oscillator the oscillator is a sawtooth waveform, providing for leading edge modulation with 350ns minimum pwm off-time. the oscillator (sawtooth) waveform has a dc offset of 1.0v. each channel?s peak-to-peak of the ramp amplit ude is set proportional to the voltage applied, which is corresponding the en/vff pin. see ? voltage feed-forward ? on page 25 . frequency synchronization and phase lock loop the fsync pin has two primary capabilities: fixed frequency operation and synchronized freque ncy operation. by connecting a resistor (r fsync ) to gnd from the fsync pin, the switching frequency can be set at any frequency between 150khz and 1.5mhz. the value of r fsync can be estimated using equation 16. the frequency setting curve shown in figure 28 is also provided to assist in selecting the correct value for r fsync. figure 25. typical upper-gate drive turn-on path figure 26. typical lower-gate drive turn-on path p ic vin pvcc ? () i vin ? p dr + = i vin q g1 n q1 ? v gs1 --------------------------- q g2 n q2 ? v gs2 --------------------------- + ?? ?? ?? pvcc f ? sw i q_vin + ? = (eq. 15) p dr p dr_up p dr_low + = (eq. 16) p dr_up r hi1 r hi1 r ext1 + ----------------------------------- r lo1 r lo1 r ext1 + ------------------------------------ - + ?? ?? ?? p qg_q1 2 ------------------- ? = p dr_low r hi2 r hi2 r ext2 + ----------------------------------- r lo2 r lo2 r ext2 + ------------------------------------ - + ?? ?? ?? p qg_q2 2 ------------------- ? = r ext2 r g1 r gi1 n q1 ------------ + = r ext2 r g2 r gi2 n q2 ------------ + = p qg_q1 q g1 pvcc 2 ? v gs1 ---------------------------------- - f sw ? n q1 ? = p qg_q2 q g2 pvcc 2 ? v gs2 ---------------------------------- - f sw ? n q2 ? = q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 gnd lgate figure 27. allowed maximum gate charge vs input voltage 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.00 q g_total fsw t a = +20c t a = +85c input voltage (v) 5 7 9 11 13 15 17 19 21 23 25 27 29
ISL8126 34 fn7892.0 september 7, 2011 . by connecting the fsync pin to an external square pulse waveform (such as the clock signal, typically 50% duty cycle from another ISL8126), the ISL8126 will synchronize its switching frequency to the fundamental frequency of the input waveform. the maximum voltage to the fsync pin is vcc + 0.3v. the frequency synchronization feature will synchronize the leading edge of clkout signal with the falling edge of channel 1?s pwm clock signal. the clkout is not available until the pll locks. the locking time is typically 130s for f sw = 500khz. en/vff1 is pulled down internally until the fs ync stabilized and the pll is in locking. the pll circuits contro l only en/vff1, and control the delay time of channel 2?s soft-start. therefore, it is recommended to connect all en/vff pins together in multiphase configuration. the loss of a synchronization signal for 13 clock cycles causes the ic to be disabled until the pll returns locking, at which point a soft-start cycle is initiated and normal operation resumes. holding fsync low will disable the ic. differential amplifier for remote sensing the differential remote sense buffers help compensate the droop due to load on the positive and negative rails and maintain the high system accuracy of 0.6%. they have precision unity gain resistor matching networks, whic h has a ultra low offset of 1mv. the output of the remote sense buffer is connected directly to the internal ov/uv comparator. as a re sult, a resistor divider should be placed on the input of the buffer for proper regulation, as shown in figure 29. the vmon pin should be connected to the fb pin by a standard feedback network. the output voltage can be set by using equation 18: to optimize system accuracy, it is highly recommended to include this impedance into calculation and use resistor with resistance as low as possible for the lower leg (r os ) of the feedback resistor divider. note that any rc filter at the inputs of the differential amplifier, will cont ribute as a pole to the overall loop compensation. figure 28. r fs vs switching frequency 0 200 400 600 800 1,000 1,200 1,400 1,600 20 40 60 80 100 120 140 160 180 200 220 240 260 r_fs (k ) switching frequency (khz) r fsync k [] 4.671 4 10 fsw khz [] 1.04 ? ? = (eq. 17) vsen- vsen+ comp fb vmon r fb r os z fb z comp ov/uv error amp comp c sen 400mv vcc figure 29. simplified remote sensing implementation v ref 10 10 vout (local) gnd (local) vsense+ (remote) gain=1 vsense- (remote) pgood pgood v out v ref 1 r fb r os ---------- + ?? ?? ?? ? = (eq. 18) figure 30. equivalent differential amplifer 20k 20k 20k 20k r dif = -500k vsen- vsen+ vcc i = vsen+ + 1.16a 40k 1.16a
ISL8126 35 fn7892.0 september 7, 2011 as some applications will not need the differential remote sense, the output of the remote sense buffer can be disabled and be placed in high impedance by pulling vsen- within 400mv of vcc. thus, the vmon pin can be used as an additional monitor of the output voltage with a resistor divider to protect the system against single point of failure, which occurs in the system using the same resistor divider for the uv/ov comparator and the output regulation. the resistor di vider ratio should be the same as the one for the output regulation so that the correct voltage information is provided to the ov/uv comparator. figure 31 shows the differential sense amplifier can be directly used as a monitor without pulling vsen- high. internal reference and system accuracy the internal reference is set to 0.6v. including bandgap variation and offset of differential and erro r amplifiers, it has an accuracy of 0.6% over commercial temperature range, and 0.9% over industrial temperature range. while the remote sense is not used, its offset (v os_da ) should be included in the tolerance calculation. equations 18 and 19 show the worst case of system accuracy calculation. v os_da should set to zero when the differential amplifier is in the loop, the differential amplifier?s input impedance (r dif ) is typically -600k with a tolerance of 20% (rdif%) and can be neglected when r os is less than 100 . to set a precision setpoint, r os can be scaled by two paralleled resistors. figure 32 shows the tolerance of various output voltage regulation for 1%, 0.5%, and 0.1% feedback resistor dividers. note that the farther the output voltage setpoint away from the internal reference voltage, the larger the tolerance; the lower the resistor tolerance (r%), the tighter the regulation. gnd vsen+ vsen- fb vmon r fb r os ov/uv error amp comp 400mv vcc figure 31. dual output voltage sense for single point of failure protection v ref vout gain=1 pgood pgood z comp r os comp r fb %min vref 1 ref% ? () ? v os_da ? () 1 r fb 1r% ? () ? r osmax ------------------------------------- - + ?? ?? ?? ? = r osmax 1 1 r os 1r% + () ? -------------------------------------- - 1 r dif 1r dif % + () ? ------------------------------------------------ - + ---------------------------------------------------------------------------------------------- - = (eq. 19) %max vref 1 ref% ? () ? v os_da ? () 1 r fb 1r% ? () ? r osmin ------------------------------------- - + ?? ?? ?? ? = r osmin 1 1 r os 1r ? % () ? ----------------------------------- - 1 r dif 1r dif ? % () ? --------------------------------------------- - + ----------------------------------------------------------------------------------------- = (eq. 20) output regulation (%) output voltage (v) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 1% 0.5% 0.5% 0.1% 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 r% = 1% 0.1% figure 32. output regulation with different resistor tolerance for ref% = 0.6%
ISL8126 36 fn7892.0 september 7, 2011 ddr and dual mode operation when ISL8126 is used in dual-output mode, the clkout/refin pin is an input signal pin. if the clkout/refin is less than 29% of vcc, an external soft-start ramp (0.6v) can be in parallel with channel 2s internal soft-start ramp for ddr/tracking applications (ddr mode). the output voltage (typical vtt ou tput) of channel 2 tracks with the input voltage (typical vddq *(1+k) from channel 1) at the clkout/refin pin. as for the exte rnal input signal and internal reference signal (ramp and 0.6v), the one with the lowest voltage will be the one to be used as the reference compared with the fb signal. so in ddr configuration, vtt channel should start-up later after its internal soft-start ramp, in which way, the vtt will track the voltage on refin pin deri ved from vddq. this can be achieved by adding more filter ing at en/vff1 compared with en/vff2. since the uv/ov comparator uses the same internal reference 0.6v to guarantee uv/ov and pre-ch arged start-up functions of channel 2, the target voltage deri ved from channel 1 (vddq) should be scaled close to 0.6v, and it is suggested to be slightly above (+2%) 0.6v with an external resi stor divider, which will have channel 2 use the internal 0.6v reference after soft-start. any capacitive load at the refin pin should not slow down the ramping of this input 150mv lower than the channel 2?s internal ramp. otherwise, the uv protection could be fault triggered prior to the end of the soft-start. the start-up of channel 2 can be delayed to avoid such a situation from happening, if high capacitive load presents at refin pin for noise decoupling. du ring shutdown, channel 2 will follow channel 1 until both channels drops below 87%, at which point both channels enter uv protection zone. depending on the loading, channel 1 might drop faster than channel 2. to solve this race condition, channel 2 can either power up from channel 1 or bridge the channel 1 output with a high current schottky diode. if the system requires to shutdown both channels when either has a fault, tying en/vff1 and en/vff2 will do the job. in ddr mode, channel 1 delays 60 over channel 2. in dual mode, depending upon the resistor divider level of refin from vcc, the ISL8126 operates as a dual-pwm controller for two independent regulators with a phase shift, as shown in table 3. the phase shift is latched as vcc raises above por and cannot be changed on the fly. layout considerations mosfets switch very fast and effi ciently. the speed at which the current transitions from one devi ce to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit an d lead to device overvoltage stress. careful component sele ction, layout, and placement minimizes these voltage spikes. consider, as an example, the turnoff transition of the upper pw m mosfet. prior to turnoff, the upper mosfet was carrying current. during the turnoff, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces mini mize the magnitude of voltage spikes. there are two sets of critical components in a dc/dc converter using a ISL8126 controller. the power components are the most critical because they switch large amounts of energy. next, are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. the power components should be placed first, which include the mosfets, input and output capacitors, and the inductors. it is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. symmetrical layout allows heat to be dissipated equally across all power trains. equidistant plac ement of the controller to the power trains (it controls throug h the integrated drivers), helps keep the gate drive traces equally short, resulting in equal trace impedances and similar drive capability of all sets of mosfets. when placing the mosfets, try to keep the source of the upper fets and the drain of the lower fets as close as thermally possible. input high-frequency capacitors, c hf , should be placed close to the drain of the upper fe ts and the source of the lower fets. input bulk capacitors, c bulk , case size typically limits following the same rule as the high-frequency input capacitors. place the input bulk capacitors as close to the drain of the upper fets as possible and minimize the distance to the source of the lower fets. locate the output inductors and output capacitors between the mosfets and the load. the high-frequency output decoupling capacitors (ceramic) should be pl aced as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to gnd next or on the capacitor solder pad. table 3. mode decoding refin range phase for channel 2 wrt channel 1 required refin ddr <29% of vcc -60 0.6v dual 29% to 45% of vcc 0 37% vcc dual 45% to 62% of vcc 90 53% vcc dual 62% to vcc 180 vcc 400mv figure 33. simplified ddr implementation phase-shifted clock vcc clkout/refin vsen2- vddq r k vtt 0.6v ----------- - 1 ? = k*r internal ss ISL8126 state machine e/a2 0.6v fb2
ISL8126 37 fn7892.0 september 7, 2011 the critical small components include the bypass capacitors (c filter ) for vcc and pvcc, and many of the components surrounding the controller including the feedback network and current sense components. locate the vcc/pvcc bypass capacitors as close to the ISL8126 as possible. it is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to emi pick-up. a multi-layer printed circuit board is recommended. dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to output inductors short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. routing ugate, lgate, and phase traces great attention should be paid to routing the ugate, lgate, and phase traces since they drive the power train mosfets using short, high current pulses. it is important to size them as large and as short as possible to redu ce their overall impedance and inductance. they should be sized to carry at least one ampere of current (0.02? to 0.05?). going be tween layers with vias should also be avoided, but if so, use two vias for interconnection when possible. extra care should be given to the lgate traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibility of shoot-through. it is also important to route each channels ugate and phase traces in as close proximity as possible to reduce their inductances. current sense component placement and trace routing one of the most critical aspects of the ISL8126 regulator layout is the placement of the inductor dcr current sense components and traces. the r-c current sens e components must be placed as close to their respective isen a and isenb pins on the ISL8126 as possible. the sense traces that connect the r-c sense components to each side of the output inductors sh ould be routed away from the noisy switching components. these traces should be routed side by side, and they should be very thin traces. it?s important to route these traces as far away from any other noisy traces or planes as possible. these traces sh ould pick up as little noise as possible. these traces should also originate from the geometric center of the inductor pin pads and that location should be the single point of contact the trace makes with its respective net. general powerpad design considerations the following is an example of how to use vias to remove heat from the ic. it is recommended to fill the ther mal pad area with vias. a typical via array fills the thermal pad foot print such that their centers are 3x the radius apart from each other. keep the vias small but not so small that their inside di ameter prevents solder wicking through during reflow. connect all vias to the ground plane. it is important the vias have a low thermal resistance for ef ficient heat transfer. it is important to have a complete co nnection of the plated-through hole to each plane. figure 34. pcb via pattern
ISL8126 38 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7892.0 september 7, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL8126 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 09/07/2011 fn7892.0 initial release
ISL8126 39 fn7892.0 september 7, 2011 package outline drawing l32.5x5b 32 lead quad flat no-lead plastic package rev 3, 5/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 index area 3 .30 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 30 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) + 0.07 - 0.05 17 25 24 8 1 32

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